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? semiconductor components industries, llc, 2005 october, 2005 ? rev. 6 1 publication order number: mc34023/d mc34023, mc33023 high speed single?ended pwm controller the mc34023 series are high speed, fixed frequency , single?ended pulse width modulator controllers optimized for high frequency operation. they are specifically designed for off?line and dc?to?dc converter applications offering the designer a cost?effective solution with minimal external components. these integrated circuits feature an oscillator, a temperature compensated reference, a wide bandwidth error amplifier, a high speed current sensing comparator, and a high current totem pole output ideally suited for driving a power mosfet. also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle?by?cycle current limiting, and a latch for single pulse metering. the flexibility of this series allows it to be easily configured for either current mode or voltage mode control. features ? 50 ns propagation delay to output ? high current totem pole output ? wide bandwidth error amplifier ? fully?latched logic with double pulse suppression ? latching pwm for cycle?by?cycle current limiting ? soft?start control with latched overcurrent reset ? input undervoltage lockout with hysteresis ? low startup current (500 a typ) ? internally trimmed reference with undervoltage lockout ? 90% maximum duty cycle (externally adjustable) ? precision trimmed oscillator ? voltage or current mode operation to 1.0 mhz ? functionally similar to the uc3823 ? pb?free packages are available* error amp oscillator 16 v ref clock r t c t ramp error amp output inverting input soft?start soft?start latching pwm ground 10 9 current limit/ shutdown power ground v c v cc uvlo 5.1v reference current limit ref this device contains 176 active transistors. output noninverting input 4 5 6 7 3 2 1 8 15 13 14 11 12 figure 1. simplified application marking diagrams 1 16 pdip?16 p suffix case 648 1 16 soic?16w dw suffix case 751g 1 16 mc34023p awlyywwg mc33023dw awlyywwg pin connections (top view) error amp noninverting input soft?start ramp c t r t clock error amp output error amp inverting input current limit/ shutdown current limit reference power ground output v cc v ref 11 5 2 1 9 10 12 13 14 15 16 8 7 6 4 3 ground v c see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package 16 1
mc34023, mc33023 http://onsemi.com 2 ordering information device package shipping ? mc33023dw soic?16w 47 units / rail MC33023DWG soic?16w (pb?free) 47 units / rail mc33023dwr2 soic?16w 1000 units / reel mc33023dwr2g soic?16w (pb?free) 1000 units / reel mc34023p pdip?16 25 units / rail mc34023pg pdip?16 (pb?free) 25 units / rail ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. maximum ratings rating symbol value unit power supply voltage v cc 30 v output driver supply voltage v c 20 v output current, source or sink (note 1) dc pulsed (0.5 s) i o 0.5 2.0 a current sense, soft?start, ramp, and error amp inputs v in ?0.3 to +7.0 v error amp output and soft?start sink current i o 10 ma clock and r t output current i co 5.0 ma power dissipation and thermal characteristics so?16l package (case 751g) maximum power dissipation @ t a = + 25 c thermal resistance, junction?to?air dip package (case 648) maximum power dissipation @ t a = + 25 c thermal resistance, junction?to?air p d r ja p d r ja 862 145 mw c/w 1.25 100 w c/w operating junction temperature t j +150 c operating ambient temperature (note 2) mc34023 mc33023 t a 0 to +70 ?40 to +105 c storage temperature range t stg ?55 to +150 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected.
mc34023, mc33023 http://onsemi.com 3 electrical characteristics (v cc = 15 v, r t = 3.65 k , c t = 1.0 nf, for typical values t a = + 25 c, for min/max values t a is the operating ambient temperature range that applies [note 2], unless otherwise noted.) characteristic symbol min typ max unit reference section reference output voltage (i o = 1.0 ma, t j = + 25 c) v ref 5.05 5.1 5.15 v line regulation (v cc = 10 v to 30 v) reg line ? 2.0 15 mv load regulation (i o = 1.0 ma to 10 ma) reg load ? 2.0 15 mv temperature stability t s ? 0.2 ? mv/ c total output variation over line, load, and temperature v ref 4.95 ? 5.25 v output noise voltage (f = 10 hz to 10 khz, t j = + 25 c) v n ? 50 ? v long term stability (t a = +125 c for 1000 hours) s ? 5.0 ? mv output short circuit current i sc ? 30 ?65 ?100 ma oscillator section frequency t j = + 25 c line (v cc = 10 v to 30 v) and temperature (t a = t low to t high ) f osc 380 370 400 400 420 430 khz frequency change with voltage (v cc = 10 v to 30 v) f osc / v ? 0.2 1.0 % frequency change with temperature (t a = t low to t high ) f osc / t ? 2.0 ? % sawtooth peak voltage v osc(p) 2.6 2.8 3.0 v sawtooth valley voltage v osc(v) 0.7 1.0 1.25 v clock output voltage high state low state v oh v ol 3.9 ? 4.5 2.3 ? 2.9 v error amplifier section input offset voltage v io ? ? 15 mv input bias current i ib ? 0.6 3.0 a input offset current i io ? 0.1 1.0 a open?loop voltage gain (v o = 1.0 v to 4.0 v) a vol 60 95 ? db gain bandwidth product (t j = + 25 c) gbw 4.0 8.3 ? mhz common mode rejection ratio (v cm = 1.5 v to 5.5 v) cmrr 75 95 ? db power supply rejection ratio (v cc = 10 v to 30 v) psrr 85 110 ? db output current, source (v o = 4.0 v) output current, sink (v o = 1.0 v) i source i sink 0.5 1.0 3.0 3.6 ? ? ma output voltage swing, high state (i o = ? 0.5 ma) output voltage swing, low state (i o = 1 ma) v oh v ol 4.5 0 4.75 0.4 5.0 1.0 v slew rate sr 6.0 12 ? v/ s pwm comparator section ramp input bias current i ib ? ?0.5 ?5.0 a duty cycle, maximum duty cycle, minimum dc (max) dc (min) 80 ? 90 ? ? 0 % zero duty cycle threshold voltage pin 3(4) (pin 7(9) = 0 v) v th 1.1 1.25 1.4 v propagation delay (ramp input to output, t j =+25 c) t plh(in/out) ? 60 100 ns soft?start section charge current (v soft?start = 0.5 v) i chg 3.0 9.0 20 a discharge current (v soft?start = 1.5 v) i dischg 1.0 4.0 ? ma 1. maximum package power dissipation limits must be observed. 2. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. t low =0 c for mc34023 t high = +70 c for mc34023 =?40 c for mc33023 = +105 c for mc33023
mc34023, mc33023 http://onsemi.com 4 electrical characteristics (v cc = 15 v, r t = 3.65 k , c t = 1.0 nf, for typical values t a = + 25 c, for min/max values t a is the operating ambient temperature range that applies [note 3], unless otherwise noted.) characteristic symbol min typ max unit current sense section input bias current (pin 9(12) = 0 v to 4.0 v) i ib ? ? 15 a current limit comparator input offset voltage (pin 11(14) = 1.1 v) v io ? ? 45 mv current limit reference input common mode range (pin 11(14)) t j =+25 c v cmr 1.0 ? 3.0 v shutdown comparator threshold v th 1.25 1.40 1.55 v propagation delay (current limit/shutdown to output, t j =+25 c) t plh(in/out) ? 50 80 ns output section output voltage low state (i sink = 20 ma) (i sink = 200 ma) high state (i source = 20 ma) (i source = 200 ma) v ol v oh ? ? 13 12 0.25 1.2 13.5 13 0.4 2.2 ? ? v output voltage with uvlo activated (v cc = 6.0 v, i sink = 0.5 ma) v ol(uvlo) ? 0.25 1.0 v output leakage current (v c = 20 v) i l ? 100 500 a output voltage rise time (c l = 1.0 nf, t j = + 25 c) t r ? 30 60 ns output voltage fall time (c l = 1.0 nf, t j = + 25 c) t f ? 30 60 ns undervoltage lockout section startup threshold (v cc increasing) v th(on) 8.8 9.2 9.6 v uvlo hysteresis voltage (v cc decreasing after turn?on) v h 0.4 0.8 1.2 v total device power supply current startup (vcc = 8.0 v) operating i cc ? ? 0.5 20 1.2 30 ma 3. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. t low =0 c for mc34023 t high = +70 c for mc34023 =?40 c for mc33023 = +105 c for mc33023
mc34023, mc33023 http://onsemi.com 5 1.0 mhz 400 khz 50 khz gain phase 2 4 6 8 9 ?55 ?25 0 25 50 75 10 k a vol , open loop voltage gain (db) , oscillator frequency (khz) f osc figure 2. timing resistor versus oscillator frequency , timing resistor ( ) 10 4 10 5 10 6 10 7 f osc , oscillator frequency (hz) figure 3. oscillator frequency versus temperature t a , ambient temperature ( c) figure 4. error amp open loop gain and phase versus frequency 10 100 1.0 k 10 k 100 k 1.0 m 10 m f, frequency (hz) v figure 5. pwm comparator zero duty cycle threshold voltage versus temperature ?55 ?25 0 25 50 75 100 t a , ambient temperature ( c) figure 6. error amp small signal transient response figure 7. error amp large signal transient response r t 125 0 45 90 135 , excess phase ( c) th , zero duty cycle (v) 0.1 s/div 0.1 s/div v cc = 15 v t a = + 25 c ct = 1. 100 nf 2. 47 nf 3. 22 nf 4. 10 nf 5. 4.7 nf 6. 2.2 nf 7. 1.0 nf 8. 470 pf 9. 220 pf 100 1000 100 k 1 3 5 7 100 125 v cc = 15 v pin 7(9) = 0 v v cc = 15 v r t = 3.6 k c t = 1.0 nf r t = 1.2 k c t = 1.0 nf r t = 36 k c t = 1.0 nf 1200 1000 800 600 400 200 0 1.30 1.28 1.26 1.24 1.22 1.20 1.0 k 470 120 100 80 60 40 20 0 ?20 2.55 v 2.5 v 2.45 v 3.0 v 2.5 v 2.0 v
mc34023, mc33023 http://onsemi.com 6 , current limit input offset voltage ( m v) v io v cc = 15 v 0 10 20 30 40 50 t a , ambient temperature ( c) , reference short circuit current (m a figure 8. reference voltage change versus source current , reference voltage change ( m v) i source , source current (ma) figure 9. reference short circuit current versus temperature ?55 t a , ambient temperature ( c) ?25 0 25 50 75 100 125 figure 10. reference line regulation figure 11. reference load regulation figure 12. current limit comparator input offset voltage versus temperature t a , ambient temperature ( c) figure 13. shutdown comparator threshold voltage versus temperature ?55 ?25 25 50 75 100 125 ?55 ?25 0 25 50 75 125 v ref i sc 100 0 t a = + 25 c t a = ?55 c v ref line regulation 10 v to 24 v (2.0 ms/div) 2.0 mv/div v ref load regulation 1.0 ma to 10 ma (2.0 ms/div) 2.0 mv/div t a = +125 c v cc = 15 v , threshold voltage (v) v th v cc = 15 v v cc = 15 v pin 11(14) = 1.1 v 1.42 100 60 20 ?20 ?60 ?100 0 ?5.0 ?10 ?15 ?20 ?25 ?30 66 65.6 65.2 64.8 64.4 64 1.50 1.46 1.38 1.34 1.30
mc34023, mc33023 http://onsemi.com 7 source saturation (load to ground) v cc ground sink saturation (load to v cc ) r t = 3.65 k c t = 1.0 nf v cc decreasing v cc increasing t a , ambient temperature ( c) , output saturation voltage (v) figure 14. soft?start charge current versus temperature a) ?55 ?25 0 25 50 75 100 125 i o , output load current (a) figure 15. output saturation voltage versus load current 0 0.2 0.4 0.6 0.8 1.0 figure 16. drive output rise and fall time figure 17. drive output rise and fall time v cc , supply voltage (v) 0 4.0 8.0 12 16 20 , supply current (ma) i chg , soft-start charge current ( v sat i cc figure 18. supply voltage versus supply current output rise & fall time 1.0 nf load 50 ns/div output rise & fall time 10 nf load 50 ns/div v cc = 15 v 80 s pulsed load 120 hz rate t a = 25 c v cc = 15 v 0 2.0 1.0 10 9.5 9.0 8.5 8.0 7.5 7.0 ?1.0 ?2.0 0 30 25 20 15 10 5.0 0
mc34023, mc33023 http://onsemi.com 8 ground 10 v ref uvlo 4.2 v figure 19. representative block diagram current limit reference 0.5 v q 9 11 12 14 13 15 pwm latch soft?start latch v in 9.2 v v cc uvlo shutdown current limit s r reference regulator v cc current limit/shutdown power ground output v c v cc + 16 4 5 6 7 3 2 1 8 c ss 9.0 a error amp pwm comparator oscillator q s r v ref r t c t noninverting input inverting input error amp output ramp soft?start 1.25 v 1.4 v clock figure 20. current limit operating waveforms output pwm comparator soft?start error amp output ramp clock c t
mc34023, mc33023 http://onsemi.com 9 operating description the mc33023 and mc34023 series are high speed, fixed frequency, single?ended pulse width modulator controllers optimized for high frequency operation. they are specifically designed for off?line and dc?to?dc converter applications offering the designer a cost ef fective solution with minimal external components. a representative block diagram is shown in figure 19. oscillator the oscillator frequency is programmed by the values selected for the timing components r t and c t . the r t pin is set to a temperature compensated 3.0 v. by selecting the value of r t , the charge current is set through a current mirror for the timing capacitor c t . this charge current runs continuously through c t . the dischar ge current is ratioed to be 10 times the charge current, which yields the maximum duty cycle of 90%. c t is charged to 2.8 v and discharged to 1.0 v. during the discharge of c t , the oscillator generates an internal blanking pulse that resets the pwm latch and, inhibits the outputs. the threshold voltage on the oscillator comparator is trimmed to guarantee an oscillator accuracy of 5.0% at 25 c. additional dead time can be added by externally increasing the charge current to c t as shown in figure 24. this changes the charge to discharge ratio of c t which is set internally to i charge /10 i charge . the new charge to discharge ratio will be: % deadtime i additiona l i charge 10 (i charge ) a bidirectional clock pin is provided for synchronization or for master/slave operation. as a master, the clock pin provides a positive output pulse during the discharge of c t . as a slave, the clock pin is an input that resets the pwm latch and blanks the drive output, but does not discharge c t . therefore, the oscillator is not synchronized by driving the clock pin alone. figures 28, 29 and 30 provide suggested synchronization. error amplifier a fully compensated error amplifier is provided. it features a typical dc voltage gain of 95 db and a gain bandwidth product of 8.3 mhz with 75 degrees of phase margin (figure 4). typical application circuits will have the noninverting input tied to the reference. the inverting input will typically be connected to a feedback voltage generated from the output of the switching power supply. both inputs have a common mode voltage (v cm ) input range of 1.5 v to 5.5 v. the error amplifier output is provided for external loop compensation. soft?start latch soft?start is accomplished in conjunction with an external capacitor. the soft?start capacitor is charged by an internal 9.0 a current source. this capacitor clamps the output of the error amplifier to less than its normal output voltage, thus limiting the duty cycle. the time it takes for a capacitor to reach full charge is given by: t (4.5 ? 10 5 )c soft-start a soft?start latch is incorporated to prevent erratic operation of this circuitry. two conditions can cause the soft?start circuit to latch so that the soft?start capacitor stays discharged. the first condition is activation of an undervoltage lockout of either v cc or v ref . the second condition is when current sense input exceeds 1.4 v. since this latch is ?set dominant?, it cannot be reset until either of these signals is removed and, the voltage at c soft?start is less than 0.5 v. pwm comparator and latch a pwm circuit typically compares an error voltage with a ramp signal. the outcome of this comparison determines the state of the output. in voltage mode operation the ramp signal is the voltage ramp of the timing capacitor. in current mode operation the ramp signal is the voltage ramp induced in a current sensing element. the ramp input of the pwm comparator is pinned out so that the user can decide which mode of operation best suits the application requirements. the ramp input has a 1.25 v offset such that whenever the voltage at this pin exceeds the error amplifier output voltage minus 1.25 v, the pwm comparator will cause the pwm latch to set, disabling the outputs. once the pwm latch is set, only a blanking pulse by the oscillator can reset it, thus initiating the next cycle. current limiting and shutdown a pin is provided to perform current limiting and shutdown operations. two comparators are connected to the input of this pin. the reference voltage for the current limit comparator is not set internally. a pin is provided so the user can set the voltage. when the voltage at the current limit input pin exceeds the externally set voltage, the pwm latch is set, disabling the output. in this way cycle?by?cycle current limiting is accomplished. if a current limit resistor is used in series with the power devices, the value of the resistor is found by: r sense i limit reference voltage i pk (switch) if the voltage at this pin exceeds 1.4 v, the second comparator is activated. this comparator sets a latch which, in turn, causes the soft start capacitor to be discharged. in this way a ?hiccup? mode of recovery is possible in the case of output short circuits. if a current limit resistor is used in series with the output devices, the peak current at which the controller will enter a ?hiccup? mode is given by: i shutdown 1.4 v r sense
mc34023, mc33023 http://onsemi.com 10 in certain applications, it may be desirable to disable the current limit comparator. this can be accomplished by biasing pin 11 to a level greater than 1.4 v but less than 3.0 v. under these conditions, the shutdown comparator and soft?start latch are activated during an overcurrent event causing the converter to enter an hiccup mode. undervoltage lockout there are two undervoltage lockout circuits within the ic. the first senses v cc and the second v ref . during power?up, v cc must exceed 9.2 v and v ref must exceed 4.2 v before the outputs can be enabled and the soft?start latch released. if v cc falls below 8.4 v or v ref falls below 3.6 v, the outputs are disabled and the soft?start latch is activated. when the uvlo is active, the part is in a low current standby mode allowing the ic to have an of f?line bootstrap startup circuit. typical startup current is 500 a. output the mc34023 has a high current totem pole output specifically designed for direct drive of power mosfets. it is capable of up to 2.0 a peak drive current with a typical rise and fall time of 30 ns driving a 1.0 nf load. separate pins for v c and power ground are provided. with proper implementation, a significant reduction of switching transient noise imposed on the control circuitry is possible. the separate v c supply input also allows the designer added flexibility in tailoring the drive voltage independent of v cc . reference a 5.1 v bandgap reference is pinned out and is trimmed to an initial accuracy of 1.0% at 25 c. this reference has short circuit protection and can source in excess of 10 ma for powering additional control system circuitry. design considerations do not attempt to construct the converter on wire?wrap or plug?in prototype boards. with high frequency, high power, switching power supplies it is imperative to have separate current loops for the signal paths and for the power paths. the printed circuit layout should contain a ground plane with low current signal and high current switch and output grounds returning on separate paths back to the input filter capacitor. shown in figure 36 is a printed circuit layout of the application circuit. note how the power and ground traces are run. all bypass capacitors and snubbers should be connected as close as possible to the specific part in question. the pc board lead lengths must be less than 0.5 inches for effective bypassing for snubbing. instabilities in current mode control, an instability can be encountered at any given duty cycle. the instability is caused by the current feedback loop. it has been shown that the instability is caused by a double pole at half the switching frequency. if an external ramp (s e ) is added to the on?time ramp (s n ) of the current?sense waveform, stability can be achieved. one must be careful no t to add too much ramp compensation. if too much is added the system will start to perform like a voltage mode regulator. all benefits of current mode control will be lost. figure 26 is an example of one way in which external ramp compensation can be implemented. 1.25 v figure 21. ramp compensation current signal s n ramp compensation ramp input ramp compensation s e a simple equation can be used to calculate the amount of external ramp slope necessary to add that will achieve stability in the current loop. for the following equations, the calculated values for the application circuit in figure 35 are also shown. s e v o l n s n p (r s )a i where: = dc output voltage = number of power transformer primary = or secondary turns = gain of the current sense network = (see figures 24 and 25) = output inductor = current sense resistance v o n p , n s a i l r s = 0.115 v/ms for the application circuit: s e 5 1.8 2 8 ( 0.3 )( 0.55 )
mc34023, mc33023 http://onsemi.com 11 pin function description pin dip/soic function description 1 error amp inverting input this pin is usually used for feedback from the output of the power supply. 2 error amp noninverting input this pin is used to provide a reference in which an error signal can be produced on the output of the error amp. usually this is connected to v ref , however an external reference can also be used. 3 error amp output this pin is provided for compensating the error amp for poles and zeros encountered in the power supply system, mostly the output lc filter. 4 clock this is a bidirectional pin used for synchronization. 5 r t the value of r t sets the charge current through timing capacitor, c t . 6 c t in conjunction with r t , the timing capacitor sets the switching frequency. 7 ramp input for voltage mode operation this pin is connected to c t . for current mode operation this pin is connected through a filter to the current sensing element. 8 soft?start a capacitor at this pin sets the soft?start time. 9 current limit/ shutdown this pin has two functions. first, it provides cycle?by?cycle current limiting. second, if the current is excessive, this pin will reinitiate a soft?start cycle. 10 ground this pin is the ground for the control circuitry. 11 current limit reference input this pin voltage sets the threshold for cycle?by?cycle current limiting. 12 power ground this is a separate power ground return that is connected back to the power source. it is used to reduce the effects of switching transient noise on the control circuitry. 13 v c this is a separate power source connection for the outputs that is connected back to the power source input. with a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. 14 output this is a high current totem pole output. 15 v cc this pin is the positive supply of the control ic. 16 v ref this is a 5.1 v reference. it is usually connected to the noninverting input of the error amplifier. output voltage feedback input 2 1 3 7 6 5 4 1.25 v oscillator v ref c t figure 22. voltage mode operation in voltage mode operation, the control range on the output of the error amplifier from 0% to 90% duty cycle is from 2.25 v to 4.05 v. v ref output voltage feedback input 2 1 3 7 6 5 4 1.25 v oscillator c t from current sense element figure 23. current mode operation in current mode control, an rc filter should be placed at the ramp input to filter the leading edge spike caused by turn?on of a power mosfet.
mc34023, mc33023 http://onsemi.com 12 figure 24. resistive current sensing i sense 9 the addition of an rc filter will eliminate instability caused by the leading edge spike on the current waveform. this sense signal can also be used at the ramp input pin for current mode control. for ramp compensation it is necessary to know the gain of the current feedback loop. if a transformer is used, the gain can be calculated by: 9 figure 25. primary side current sensing r w i sense the addition of an rc filter will eliminate instability caused by the leading edge spike on the current waveform. this sense signal can also be used at the ramp input pin for current mode control. for ramp compensation it is necessary to know the gain of the current feedback loop. the gain can be calculated by: a i r sense turns ratio a i r w turns ratio 3 7 6 5 figure 26a. slope compensation (noise sensitive) oscillator c t c 1 r 1 r 2 current sense information 4 1.25 v this method of slope compensation is easy to implement, however, it is noise sensitive. capacitor c 1 provides ac coupling. the oscillator signal is added to the current signal by a voltage divider consisting of resistors r 1 and r 2 . 3 7 figure 26b. slope compensation (noise immune) current sense resistor r f c f c m 1.25 v r m ramp input output r w output r m c m r f c f 1.25 v ramp input current sense transformer 7 3 when only one output is used, this method of slope compensation can be used and it is relatively noise immune. resistor r m and capacitor c m provide the adde d s lope necessary. by choosing r m and c m with a larger time constant than the switching frequency, you can assume that its charge is linear. first choose c m , the n r m can be adjusted to achieve the required slope. the diode provides a reset pulse at the ramp input at the end of every cycle. t he charge current i m can be calculate d b y i m = c m s e . then r m can be calculated by r m = v cc /i m. figure 26.
mc34023, mc33023 http://onsemi.com 13 c t v ref r dt r t 6 5 4 oscillator figure 27. dead time addition additional dead time can be added by the addition of a dead time resistor from v ref to c t . see text on oscillator section for more information. 5.0 v 0 v c t r t 6 5 4 oscillator figure 28. external clock synchronization the sync pulse fed into the clock pin must be at least 3.9 v. r t and c t need to be set 10% slower than the sync frequency. this circuit is also used in voltage mode operation for master/slave operation. the clock signal would be coming from the master which is set at the desired operating frequency, while the slave is set 10% slower. figure 29. current mode master/slave operation over short distances 6 5 4 slave oscillator c t r t 6 5 4 master oscillator v ref 4 figure 30. synchronization over long distances master oscillator 6 5 c t r t 6 5 4 slave oscillator 16 reference c t nc 2200 1.0 k 4.7 k 20 430 1.15 r t mmbt3906 mmbd0914 mmbt3904
mc34023, mc33023 http://onsemi.com 14 v ref r 2 r 1 c ss 1 2 8 + figure 31. buffered maximum clamp level in voltage mode operation, the maximum duty cycle can be clamped. by the addition of a pnp transistor to buf fer the clamp voltage, the soft?start current is not affected by r 1 . the new equation for soft?start is t v clamp 0.6 9.0 a ( c ss ) in current mode operation, this circuit will limit the maximum voltage allowed at the ramp input to end a cycle. base charge removal v in to current sense input r s 12 14 15 0 ? + i b v c figure 32. bipolar transistor drive the totem pole output can furnish negative base current for enhanced transistor turn?off, with the addition of the capacitor in series with the base. to current sense input r s 12 14 15 v c v in figure 33. mosfet parasitic oscillations a series gate resistor may be needed to dampen high frequency parasitic oscillation caused by the mosfet?s input capacitance and any series wiring inductance in the gate?source circuit. the series resistor will also decrease the mosfet switching speed. a schottky diode can reduce the driver?s power dissipation due to excessive ringing, by preventing the output pin from being driven below ground. the schottky diode also prevents substrate injection when the output pin is driven below ground. 12 14 15 v c figure 34. isolated mosfet drive the totem pole output can easily drive pulse transformers. a schottky diode is recommended when driving inductive loads at high frequencies. the diode can reduce the driver?s power dissipation due to excessive ringing, by preventing the output pin from being driven below ground.
mc34023, mc33023 http://onsemi.com 15 + 1.0 1.2 k 16 4 5 6 7 3 1 2 8 0.01 22 k 2.0 k 47 k soft?start 0.1 1000 pf 0.015 f v ref v ref oscillator 1.25 v error r pwm comparator amp s q 9.0 a 4.2 v v ref uvlo pwm latch r s q reference regulator v cc uvlo 9.2 v 15 13 14 12 11 9 10 10 4.7 irf640 4.7 47 47 k 100 50 1600 pf 3.9 k 1.0 k 220 pf 100 47 100 1n5819 mur410 mbr2535 ctl 1500 pf 22 1.8 22 l 1 1500 pf 10 f v = 5.0 v o current limit shutdown 1.4 v 0.5 v soft?start latch 1n5819 v = 40 v to 56 v in t 1 0.3 10 primary: 8 turns #48 awg (1300 strands litz wire) secondary: 2 turns 0.003?? (2 layers) copper foil bootstrap: 1 turn added to secondary #36 awg core: philips 3f3, part #4312 020 4124 bobbin: philips part #4322 021 3525 coilcraft p3269?a 2 turns #48 awg (1300 strands litz wire) core: philips 3f3, part #ep10?3f3 bobbin: philips part #ep10pcb1?8 l = 1.8 h coilcraft p3270?a power fet: aavid heatsink #533902b02552 with clip all power devices are insulated with berquist sil?pad 150 10(1.0 f) ceramic capacitors in parallel 5(1.5 ) resistors in parallel t 1 l 1 1 2 heatsinks ? output rectifiers: aavid heatsink #533402b02552 with clip insulators ? ? ? ? ? test condition result line regulation load regulation output ripple efficiency v = 40 v to 56 v, i = 7.5a in o v = 48 v, i = 4.0 a to 7.5 a in o v = 48 v, i = 7.5 a in o v = 48 v, i = 7.5 a in o 14 mv = 0.275% 54 mv = 1.0% 10 mvp?p 69.8% 2 1 figure 35. application circuit
mc34023, mc33023 http://onsemi.com 16 6.5 (top view) 4.0 mc34023 figure 36. pc board with components 100 pf 100 pf 1000 pf 0.01 0.01 100 2200 pf +10 1n5819 1n5819 mbr 2535cti 1500 pf mbr 2535cti 1500 pf 1n5819 0.01
mc34023, mc33023 http://onsemi.com 17 (top view) figure 37. pc board without components 4.0 6.5 (bottom view)
mc34023, mc33023 http://onsemi.com 18 package dimensions pdip?16 p suffix case 648?08 issue t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ?a? b f c s h g d j l m 16 pl seating 18 9 16 k plane ?t? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 soic?16w dw suffix case 751g?03 issue c d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 q 0 7 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 mc34023/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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